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ASIC Design Engineer

Location: South Bay (Mountain View)         posted: 05.28.19

Interested candidates send resume to:  Google LLC, PO Box 26184 San Francisco, CA 94126 Attn: V. Murphy. Please reference job # below:

ASIC Design Engineer (Mountain View, CA) Design, develop, modify, &/or test hardware needed for various Google projects. #1615.36831 Exp Incl: ASIC Design-for test, synthesis, simulation & verification flow; IP integration; simulation & verification tools; STA constraints dev & analysis for Design-for test modes & SDF simulations; EDA Test tools; scripting skills in Python or Tcl; test standards; test formats; fault modeling Stuck-at, Transition, Path Delay, Gate-Exhaustive, IDDQ, & other adv Design-for test models; Design-for test specifications & driving Design-for test architecture for complex chips; Design-for test, MBIST, & ATPG tools; Silicon bring-up, debug, & validation of Design-for test features on ATE, debugging ATPG patterns, Compressed ATPG patterns, MBIST & JTAG related issues; & 16nm or smaller process nodes.

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