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Hardware Engineer

Location: South Bay (Mountain View)         posted: 09.03.19

Interested candidates send resume to:  Google LLC, PO Box 26184 San Francisco, CA 94126 Attn: V. Murphy. Please reference job # below:

Hardware Engineer (Mountain View, CA) Design, develop, modify, &/or test hardware needed for various Google projects. #1615.48327 Exp Incl: C, Shell, & Perl; Verilog & SOC implement; integrat of microcontrollers, SOC Clock & reset structuring; analyzation of perf bottlenecks in SOC fabric; SOC dsgn modifications to overcome constraints & limitations of FPGA, emulation, dsgn validation & physical dgn; ASIC dsgn methodologies, low-power dsgns, powergating, & multi-voltage dsgns; integration of complex Analog IPs; func validation & signal characterization of USB, PCIE, ADC, & temp sensor; use of oscilloscopes, signal generators, logic analyzers & protocol analyzers; ATE bench tests for USB, temp  sensor, & ADC; & I2C, GPIO, SPI, UART protocols.

#1615.42076 Exp Incl: C, C++, and Perl; Verilog, systemverilog, SOC implementation; FPGA validation & emulation, func validation, physical dsgns, & DFT methodologies; ASIC dsgn methodologies, low-power dsgns, power-gating, & multi-voltage dsgns; func ASIC dsgn verification using UVM & SVA; & sys testing, characterization, & debugging incl use of industry standard waveform viewers.

#1615.40831 Exp Incl: computer architecture; Verilog & SystemVerilog; & Perl or Python.

#1615.41358 Exp Incl: ASIC digital dsgn using Verilog; Synthesis & timing closure of digital dsgns; Clock Domain Crossing Techniques; Static Timing Analysis; & Scripting w/ Perl.

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