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Hardware Engineer

Location: South Bay (Mountain View)         posted: 07.13.20

Interested candidates send resume to:  Google LLC, PO Box 26184 San Francisco, CA 94126 Attn: V. Cheng. Please reference job # below:  

Hardware Engineer (Mountain View, CA) Design, develop, modify, &/or test hardware needed for various Google projects. #1615.38954 Exp Incl: ASIC physical design flows & method in adv process nodes; IP integration; industry std synthesis, PNR, LEC & STA tools; solving physical design challenges across various technologies; script in Python, TCL, or Perl; block & top level physical design method; extraction of design parameters, qor metrics, & analyzing trends; semiconductor device physics & transistor characteristics; & Verilog or system Verilog.  

#1615.56041 Exp Incl: Verilog; RTL design; test bench dev’t; CPU arch; verif of unit-level blocks or full chip; & write scripts to automate feature test & debug.  

#1615.50851 Exp Incl: electronic devices syst validat & test method dev; debug, troubleshoot & root cause analysis; high speed signal & broadb& signal test; simulation tools; RF syst characteriz & validation; power supply test; oscilloscope, spectrum analyzer, or netw analyzer; lab test automat; & Python or Perl. Trvl req’d.  

#1615.37956 Exp Incl: Camera image sensors & lens; AF & base band; module mfg & test; Camera module design; & Optical design tools. Trvl req’d.  

#1615.43165 Exp Incl: C, C++, or Perl; UVM & OVM; Verilog & Systemverilog; FPGA or ASIC; USB3, PCIe, or SATA; Pre-silicon verif; Test & debug; & Synopsys VCS, ModelSim, or Cadence.  

#1615.39673 Exp Incl: define, design & verify ASIC dev’t doc; arch design, logic design, & syst simulation; module interfaces/formats for simulation; SoC perf analysis; C++; DRAM memory controller arch; Computer arch; Write technical specs; dev’t of multidimensional designs involving layout of complex integrated circuits; process flow from high-level design to synthesis, place & route, & timing & power use; & analysis of equip to establish operation data, conduct experiment tests, & evaluate results.  

#1615.50793 Exp Incl: SystemVerilog & UVM; Testbench arch; OO programming; Verify processors; & Asic design verif.  

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