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ASIC Design Engineer [Multiple Positions Available]

Location: South Bay (Cupertino)         posted: 08.24.20

EMPLOYER:        Apple Inc. 

JOB TITLE:          ASIC Design Engineer [Multiple Positions Available]


JOB ID:                 7311453


JOB DESCRIPTION: Apple Inc. has multiple positions available for ASIC Design Engineers in Cupertino, California. Responsible for timing constraint development, analysis and validation for functional and test modes. Perform chip-level and block-level synthesis, Clock Domain Crossing (CDC) analysis, Clock Tree Synthesis (CTS) analysis, Full-chip Multi-Mode Multi-Corner (MMMC) Static Timing Analysis (STA). Develop signoff STA flow with Advanced On-Chip Variation (AOCV), and constraint checklist. Provide design feedback, CTS and PnR implementation guidelines to facilitate the timing closure of critical logic in the design. Perform CDC analysis and follow up with designers/IP-vendors for resolving CDC issues in a project.



To apply, mail your resume to: Apple Inc., ATTN: D.W., 1 Infinite Loop 104-1GM, Cupertino, CA 95014, with reference to Job ID: 7311453. Apple is an Equal Employment Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities.

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