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ASIC Design Engineer [Multiple Positions Available]

Location: South Bay (Cupertino)         posted: 08.08.22

EMPLOYER:        Apple Inc. 

JOB TITLE:          ASIC Design Engineer [Multiple Positions Available]

 

JOB ID:                 4244396

               

JOB DESCRIPTION: Apple Inc. has multiple positions available for ASIC Design Engineer in Cupertino, CA. Responsible for the PHY design effort interfacing with architecture, CAD, timing and logic design teams, with a critical impact on delivering best in class PHY designs. Responsible for the physical design of high performance PHY design from RTL to delivery of final GDSII. Generate block/chip level static timing constraints. Create full chip floor-plan including pin placement, partitions and power grid. Develop and validate high performance low power clock network guidelines. Perform block level place and route and close the design to meet timing, area and power constraints. Generate and Implement ECOs to fix timing, noise and EM IR violations. Run physical design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations. Assist in flow development for chip integration. Participate in establishing CAD and physical design methodologies for construction designs.

 

CONTACT: To apply, email your resume to: jobadv@apple.com, with reference to Job ID: 4244396. Apple is an Equal Employment Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities.

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