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Design Verification Engineer [Multiple Positions Available]

Location: South Bay (Cupertino)         posted: 08.29.22

EMPLOYER:        Apple Inc. 

JOB TITLE:          Design Verification Engineer  [Multiple Positions Available]

 

JOB ID:                9908614

              

JOB DESCRIPTION: Apple Inc. has multiple positions available for Design Verification Engineer in Cupertino, CA. Develop Object Oriented UVM Testbench infrastructure for IP and SoC level verification. Develop system level test plan for Wireless chipsets. Develop UVM compliant checkers, scoreboards, tests for ARM based SOC Sub-Systems. Debug RTL, generate meaningful debug information and work with DV and Design team on closing bugs. Integrate complex reference model into System Verilog and UVM based test bench for SOC sub-systems verification. Verify Low Power scenarios at block and Chip level. Develop UPF based low power test bench and verify power cycling features of SoC. Develop C based test suite to verify multi-CPU based SOC Infrastructure. Develop coverage monitors and close coverage, complete checklists, and run xPROP simulations for DV closure.  

 

CONTACT: To apply, email your resume to: jobadv@apple.com, with reference to Job ID: 9908614. Apple is an Equal Employment Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities.

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