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Design Verification Engineer [Multiple Positions Available]

Location: South Bay (Cupertino)         posted: 09.19.22

EMPLOYER:        Apple Inc.  

JOB TITLE:          Design Verification Engineer [Multiple Positions Available]

 

JOB ID:                 4431622

               

JOB DESCRIPTION: Apple Inc. has multiple positions available for Design Verification Engineers in Cupertino, CA and various unanticipated locations throughout the USA. ASIC Design and Verification of a Wireless Cellular Modem. Write Testbench or Verification Environment using Verilog, SystemVerilog, UVM, C/C++. Implement SystemVerilog Assertions (SVAs). Test plan development. Work with RTL designers for debugging test failures. Implement Random Constraints. Code and Function Coverage Analysis. Build coverage driven verification plans from specifications, review and refine to achieve coverage targets. Architect UVM based highly reusable test benches and integrate complex multi-instance VIP’s, sub-system test benches and test suites to SoC level, achieve targeted coverage, collaborate with design, architecture, Software, Firmware, and external IP delivery teams to effectively integrate and verify overall SoC design. Construct detailed test plan to cover key integration use cases, through collaborative work with design, Software, Firmware teams. Collaborate with Software, Firmware, emulation and product testing teams to aid in the verification and debugging of boot code, drivers and test vector generation; and work closely with DV methodology architects to improve verification flow.

 

CONTACT: To apply, email your resume to: jobadv@apple.com, with reference to Job ID: 4431622. Apple is an Equal Employment Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities.

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