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Design Verification Engineer [Multiple Positions Available]

Location: South Bay (Cupertino)         posted: 02.06.23

EMPLOYER: Apple Inc.

JOB TITLE:          Design Verification Engineer [Multiple Positions Available]

JOB ID: 2211559  

JOB DESCRIPTION: Apple Inc. has multiple positions available for Design Verification Engineer in Cupertino, California. Utilize Emulation for verification of ASICs (Application Specific Integrated Circuit chips). Use cutting-edge technology of bringing in mixed signal models onto the Emulation platform. Port the design onto the Palladium platform, followed by executing the detailed Emulation testplan. Bring up the emulation platform for ASICs along with their mixed signal components. Develop monitors and checkers for Emulation platform and come up with latest techniques to achieve better performance. Prepare and execute the test plan and performing reviews with the cross functional teams. Collaborate cross functionally with Design, Architecture, Power, Silicon Validation, Performance and Soft Ware Team. Develop code for Design and verification that aids with emulation activities, using Verilog/System Verilog/UVM (Universal Verification Methodology). $130,000.00- $196,500.00/yr.

CONTACT: To apply, email your resume to:, with reference to Job ID: 2211559. Apple is an Equal Employment Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities.

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