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Design Verification Engineer [Multiple Positions Available

Location: South Bay (Cupertino)         posted: 02.13.23

EMPLOYER: Apple Inc.

JOB TITLE:          Design Verification Engineer [Multiple Positions Available]

JOB ID: 7554462  

JOB DESCRIPTION: Apple Inc. has multiple positions available for Design Verification Engineers in Cupertino, California. Perform Verilog/System Verilog, digital simulation and debug. Ensuring the quality of the system on chip (SOC), and interfacing with all disciplines (vertical product model) with critical impact in getting functional products to customers. Reviewing specifications, developing attributes, testing and providing coverage plans, defining methodology and test benches, utilizing in-depth knowledge of industry standard interfaces: Verilog, Verilog simulator and debug. Working closely with design and micro-architecture teams to understand the functional and performance goals of the design. Staying abreast with design specs, conducting test plan reviews, developing block/full chip tests, and triaging failures; and Supporting gate level functional verification, running regressions, managing bug tracking, analyzing code and functional coverage. $130,000.00 - $196,500.00/yr.

CONTACT: To apply, email your resume to:, with reference to Job ID: 7554462. Apple is an Equal Employment Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities.

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