JOB DESCRIPTION: Apple Inc. has multiple positions available for ASIC Design Engineer in Cupertino, CA. Review Architecture and Design Specifications. Extract design features and develop attributes and verification plans. Work with designers to verify DFT and MBIST implementation and run various checks. Implement test benches, assertions, checkers, generating directed/constrained random tests. Debug failures, running RTL and power-aware gate level simulations, tracking bugs and closing coverage. Handle schedules and supporting cross-functional engineering effort. Assist in verification flows, automation scripts and regressions. Work with test engineers to bring up functional and structural patterns for various Analog IPs and DFT features on Silicon and support further characterization and test time optimization. Perform simulations in RTL, Gate Netlist, and With X-propagation and UPF enabled. $126,464 - $190,000/yr.
CONTACT: To apply, email your resume to: jobadv@apple.com, with reference to Job ID: 4550511. Apple is an Equal Employment Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities.
EMPLOYER: Apple Inc.
JOB TITLE: ASIC Design Engineer [Multiple Positions Available]
JOB ID: 4550511
JOB DESCRIPTION: Apple Inc. has multiple positions available for ASIC Design Engineer in Cupertino, CA. Review Architecture and Design Specifications. Extract design features and develop attributes and verification plans. Work with designers to verify DFT and MBIST implementation and run various checks. Implement test benches, assertions, checkers, generating directed/constrained random tests. Debug failures, running RTL and power-aware gate level simulations, tracking bugs and closing coverage. Handle schedules and supporting cross-functional engineering effort. Assist in verification flows, automation scripts and regressions. Work with test engineers to bring up functional and structural patterns for various Analog IPs and DFT features on Silicon and support further characterization and test time optimization. Perform simulations in RTL, Gate Netlist, and With X-propagation and UPF enabled. $126,464 - $190,000/yr.
CONTACT: To apply, email your resume to: jobadv@apple.com, with reference to Job ID: 4550511. Apple is an Equal Employment Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities.