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Sr. Staff DFT Engineer

Location: South Bay (San Jose)         posted: 06.28.24

  • High level SOC DFT architecture definition:  including SCAN, MBIST, IP tests, JTAG
  • Define and implement SOC level DFT integration (UDTR, OCC, EFuse)
  • Develop test insertion flow for scan, MBIST, JTAG
  • Estimate and achieve targeted test coverage and ATE test time
  • Develop timing constraints for all DFT modes
  • Verify test patterns pre-silicon and post-silicon
  • Write scripts in TCL, Perl, Python to achieve productivity enhancements through automation

Full-time position (1.0 Full Time Equivalent):  Hours: 9:00 am to 5:00 pm

Employer:  SiMa Technologies, Inc.

Work Location:  333 W. San Carlos Street St., Suite 1100, San Jose, CA  95110.

Salary:  $225,451.00/year


  • Master’s Degree in Electrical Engineering, or equivalent, including graduate level coursework in DFT fundamentals and logic design;
  • Four years’ experience in complex SOC level DFT
  • Two years’ experience in DFT execution in advanced finFET technology
  • Experience with EDA tools such as Synopsys, Tetramax, and VCS
  • Experience using DFT fundamentals of defect models and ATPG algorithm
  • Experience with SOC architecture and HDL languages such as Verilog
  • Scripting skills in TCL, Python
  • Experience with ATE – Automatic Test Equipment, particularly with targeted test coverage and test time requirements.

Send resume to:  People & Culture Team, SiMa Technologies, Inc., 333 W. San Carlos St., Suite 1100, San Jose, CA  95110


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