ASIC Design Engineer [Multiple Positions Available]

Apple Inc.

EMPLOYER:        Apple Inc. 

JOB TITLE:          ASIC Design Engineer [Multiple Positions Available]


JOB ID:                 0143475


JOB DESCRIPTION: Apple Inc. has multiple positions available for ASIC Design Engineers in Cupertino, California and various unanticipated locations throughout the USA. Implement power gating for mobile System-on-Chips (SOCs): power intent methodology, power intent analysis, convergence, closure, and final signoff. Code power intent for SOC blocks, implement through synthesis and P&R and validate & Sign-off implementation. Apply knowledge of detailed path analysis, understanding of chip floor planning and power domain crossings, and background in deep submicron process technology. Work with process device types, biasing requirements and derates, and detailed tool settings. Work with both Front End and Physical Design Engineers for power intent changes related to constraint debug and updates as well as detailed specifications and validation of design changes. Execute power verification runs, maintain and innovate scripts and infrastructure, and provide documentation for guidelines and specifications. Apply strong signoff ownership to ensure first silicon success.



To apply, mail your resume to: Apple Inc., ATTN: D.W., 1 Infinite Loop 104-1GM, Cupertino, CA 95014, with reference to Job ID: 0143475. Apple is an Equal Employment Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities.