ASIC Design Engineer [Multiple Positions Available]

Apple Inc.

EMPLOYER:        Apple Inc. 

JOB TITLE:          ASIC Design Engineer [Multiple Positions Available]


JOB ID:                 5016537


JOB DESCRIPTION: Apple Inc. has multiple positions available for ASIC Design Engineer in Cupertino, CA. Responsible for floorplanning, Physical Design, and signoff closure of full chip System-on-Chip (SoC) designs. Develop and test Place and Route (PnR) scripts. Design high-level PnR for SoC ASIC designs. Design and optimize integration of Intellectual Property Cores and subsystems from internal and external groups to meet performance specifications. Design interfaces between sub-blocks to achieve high frequency data transfer across the chip. Generate physical and timing constraints for sub-block implementation. Combine PnR logic with custom macros. Place synthesized netlist for optimal timing and in optimal areas. Optimize chip floorplan and placement for power, performance, and area. Generate clock distribution (clock tree synthesis) to sub-blocks and top level synchronous elements. Analyze PnR results, iterate and ensure part operation at target frequency. Ensure PnR results are manufacturable and automate PnR flow to add customization and collect metrics and results.


CONTACT: To apply, mail your resume & transcript(s) to: Apple Inc., ATTN: D.W., 1 Infinite Loop 104-1GM, Cupertino, CA 95014, with reference to Job ID: 5016537. Apple is an Equal Employment Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities.